1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
 
    wire p2_1 = p2a&p2b;
    wire p2_2 = p2c&p2d;
    wire p1_1 = p1a&p1c&p1b;
    wire p1_2 = p1f&p1e&p1d;
 
    assign p2y = p2_1 | p2_2;
    assign p1y = p1_1 | p1_2;
 
endmodule